Commit dc290df5 authored by Талибов Сэрхан Махмад Оглы's avatar Талибов Сэрхан Махмад Оглы
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Merge branch 'broker-dev' into 'master'

2 of 4 services are donwe

See merge request !1
1 merge request!12 of 4 services are donwe
Showing with 1282 additions and 0 deletions
+1282 -0
.gitignore 0 → 100644
.vs/
bin
obj
\ No newline at end of file

Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio Version 17
VisualStudioVersion = 17.9.34728.123
MinimumVisualStudioVersion = 10.0.40219.1
Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Broker", "Broker\Broker.csproj", "{878FA1BC-E0B7-4E44-8A96-BBC8A39B78EA}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|Any CPU = Debug|Any CPU
Release|Any CPU = Release|Any CPU
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{878FA1BC-E0B7-4E44-8A96-BBC8A39B78EA}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
{878FA1BC-E0B7-4E44-8A96-BBC8A39B78EA}.Debug|Any CPU.Build.0 = Debug|Any CPU
{878FA1BC-E0B7-4E44-8A96-BBC8A39B78EA}.Release|Any CPU.ActiveCfg = Release|Any CPU
{878FA1BC-E0B7-4E44-8A96-BBC8A39B78EA}.Release|Any CPU.Build.0 = Release|Any CPU
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
GlobalSection(ExtensibilityGlobals) = postSolution
SolutionGuid = {93E8500E-DF4F-40CA-856C-CB9D77B21DF9}
EndGlobalSection
EndGlobal
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<OutputType>Exe</OutputType>
<TargetFramework>net8.0</TargetFramework>
<ImplicitUsings>enable</ImplicitUsings>
<Nullable>enable</Nullable>
</PropertyGroup>
<ItemGroup>
<Compile Include="..\..\Shared\ProjectSettings.cs" Link="ProjectSettings.cs" />
</ItemGroup>
<ItemGroup>
<PackageReference Include="System.Security.Cryptography.ProtectedData" Version="9.0.2" />
</ItemGroup>
</Project>
using System;
using System.Diagnostics;
using System.Text.Json;
using System.Text.Json.Nodes;
using System.Text.Json.Serialization;
namespace HDLNoCGen
{
static class Program
{
static void uncheckMetadata (string json_path, int stage)
{
string json = File.ReadAllText(json_path);
ProjectSettings projectSettings = JsonSerializer.Deserialize<ProjectSettings>(json);
if (stage <= 3)
{
projectSettings.databaseMetadata.writtenToDB = false;
}
if (stage <= 2)
{
projectSettings.quartusMetadata.quartusCompiled = false;
}
if (stage <= 1)
{
projectSettings.graphVerilogMetadata.verilogGenerated = false;
}
if (stage == 0)
{
projectSettings.graphVerilogMetadata.graphSerialized = false;
}
json = JsonSerializer.Serialize<ProjectSettings>(projectSettings, new JsonSerializerOptions { WriteIndented = true });
File.WriteAllText(json_path, json);
}
static void Main(string[] args)
{
bool launch_manager = false;
string project_name = "";
string project_location = "";
string project_new_name = "";
string project_action = "o";
bool launch_graph = false;
string topology = "";
List<int> generators = new List<int>();
string queue_type = "";
string queue_position = "";
string arbiter_type = "";
string algorithm = "";
int info_width = 0;
int queue_length = 0;
bool create_verilog = false;
bool launch_quartus = false;
string device_name = "5CGXFC9E7F35C8";
bool launch_db = false;
string db_ip = "";
string db_username = "";
string db_password = "";
string db_name = "";
int db_port = 5432;
bool launch_settings = false;
string quartus_path = "";
try
{
for (int i = 0; i < args.Length; i++)
{
switch (args[i])
{
case "--project":
launch_manager = true;
bool project_breaker = false;
while (!project_breaker)
{
if (i + 1 < args.Length)
{
switch (args[++i])
{
case "-n":
case "--name":
project_name = args[++i];
break;
case "-l":
case "--location":
project_location = args[++i];
break;
case "-o":
case "--open":
project_action = "o";
break;
case "-c":
case "--create":
project_action = "c";
break;
case "-e":
case "--erase":
project_action = "e";
break;
case "-r":
case "--rename":
project_action = "r";
project_new_name = args[++i];
break;
default:
i--;
project_breaker = true;
break;
}
}
else
{
project_breaker = true;
}
}
break;
case "--graph":
launch_graph = true;
bool graph_breaker = false;
while (!graph_breaker)
{
if (i + 1 < args.Length)
{
switch (args[++i])
{
case "c":
topology = "c";
break;
case "m":
topology = "m";
break;
case "t":
topology = "t";
break;
case "--queue_type":
queue_type = args[++i];
break;
case "--queue_position":
queue_position = args[++i];
break;
case "--arbiter_type":
arbiter_type = args[++i];
break;
case "--algorithm":
algorithm = args[++i];
break;
case "--info_width":
try
{
info_width = Convert.ToInt32(args[++i]);
}
catch (Exception e)
{
Console.WriteLine("--info_width must be a number");
Environment.Exit(1);
}
break;
case "--queue_length":
try
{
queue_length = Convert.ToInt32(args[++i]);
}
catch (Exception e)
{
Console.WriteLine("--queue_lenght must be a number");
Environment.Exit(1);
}
break;
case "-v":
case "--verilog":
create_verilog = true;
break;
default:
try
{
generators.Add(Convert.ToInt32(args[i]));
}
catch (Exception e)
{
i--;
graph_breaker = true;
}
break;
}
}
else
{
graph_breaker = true;
}
}
break;
case "--quartus":
launch_quartus = true;
if (i + 1 < args.Length)
{
switch (args[++i])
{
case "-d":
case "--device":
device_name = args[++i];
break;
default:
i--;
break;
}
}
break;
case "--database":
launch_db = true;
bool db_breaker = false;
while (!db_breaker)
{
if (i + 1 < args.Length)
{
switch (args[++i])
{
case "-i":
case "--ip":
db_ip = args[++i];
break;
case "-u":
case "--username":
db_username = args[++i];
break;
case "--pass":
case "--password":
db_password = args[++i];
break;
case "-n":
case "--name":
db_name = args[++i];
break;
case "--port":
try
{
db_port = Convert.ToInt32(args[++i]);
}
catch (FormatException e)
{
Console.WriteLine("--port must be a number");
Environment.Exit(1);
}
break;
default:
i--;
db_breaker = true;
break;
}
}
else
{
db_breaker = true;
}
}
break;
case "--settings":
launch_settings = true;
bool settings_breaker = false;
while (!settings_breaker)
{
if (i + 1 < args.Length)
{
switch (args[++i])
{
case "--qp":
case "--quartus_path":
quartus_path = args[++i];
break;
default:
i--;
settings_breaker = true;
break;
}
}
else
{
settings_breaker = true;
}
}
break;
default:
Console.WriteLine($"Argument {args[i]} does not exist. Check the spelling or check graph generator numbers");
Environment.Exit(1);
break;
}
}
}
catch (IndexOutOfRangeException e)
{
Console.WriteLine("No argument after an option that requires an argument");
Environment.Exit(1);
}
if (launch_manager)
{
using (Process manager = new Process())
{
string manager_location = "../../../../../Project_manager/Project_manager/bin/Debug/net8.0";
string manager_arguments = $"-l {project_location} -n {project_name} -{project_action} {(project_action == "r" ? project_new_name : "")}";
string output_data = "";
manager.StartInfo.FileName = $"{manager_location}/Project_manager.exe";
manager.StartInfo.Arguments = manager_arguments;
manager.StartInfo.RedirectStandardOutput = true;
manager.StartInfo.WorkingDirectory = manager_location;
manager.OutputDataReceived += new DataReceivedEventHandler((sender, e) =>
{
if (!String.IsNullOrEmpty(e.Data))
{
output_data = $"{e.Data}\n";
}
});
manager.Start();
manager.BeginOutputReadLine();
manager.WaitForExit();
manager.Kill();
if (manager.ExitCode != 0)
{
Console.WriteLine("Project_manager failure:");
Console.Write(output_data);
Environment.Exit(1);
}
}
}
if (launch_graph)
{
uncheckMetadata($"{project_location}/{project_name}_metadata.json", 0);
using (Process veriloger = new Process())
{
string veriloger_location = "../../../../../Graph_verilog_generator/Graph_verilog_generator/bin/Debug/net8.0";
string veriloger_arguments = $"-l {project_location} -n {project_name} {topology} {String.Join(" ", generators)} " +
$"--queue_type {queue_type} " +
$"--queue_position {queue_position} " +
$"--arbiter_type {arbiter_type} " +
$"--algorithm {algorithm} " +
$"--info_width {info_width} " +
$"--queue_length {queue_length} " +
$"{(create_verilog ? "-v" : " ")}";
string output_data = "";
veriloger.StartInfo.FileName = $"{veriloger_location}/Graph_verilog_generator.exe";
veriloger.StartInfo.Arguments = veriloger_arguments;
veriloger.StartInfo.RedirectStandardOutput = true;
veriloger.StartInfo.WorkingDirectory = veriloger_location;
veriloger.OutputDataReceived += new DataReceivedEventHandler((sender, e) =>
{
if (!String.IsNullOrEmpty(e.Data))
{
output_data = $"{e.Data}\n";
}
});
veriloger.Start();
veriloger.BeginOutputReadLine();
veriloger.WaitForExit();
veriloger.Kill();
if (veriloger.ExitCode != 0)
{
Console.WriteLine("Graph_verilog_generator failure:");
Console.Write(output_data);
Environment.Exit(1);
}
}
}
}
}
}
\ No newline at end of file
{
"profiles": {
"Broker": {
"commandName": "Project",
"commandLineArgs": "--project -l D:/kal -n ultrakal -r superkal"
}
}
}
\ No newline at end of file

Microsoft Visual Studio Solution File, Format Version 12.00
# Visual Studio Version 17
VisualStudioVersion = 17.9.34728.123
MinimumVisualStudioVersion = 10.0.40219.1
Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Graph_verilog_generator", "Graph_verilog_generator\Graph_verilog_generator.csproj", "{68AA1BBD-6B31-40D4-BC74-5371E2242388}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|Any CPU = Debug|Any CPU
Release|Any CPU = Release|Any CPU
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{68AA1BBD-6B31-40D4-BC74-5371E2242388}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
{68AA1BBD-6B31-40D4-BC74-5371E2242388}.Debug|Any CPU.Build.0 = Debug|Any CPU
{68AA1BBD-6B31-40D4-BC74-5371E2242388}.Release|Any CPU.ActiveCfg = Release|Any CPU
{68AA1BBD-6B31-40D4-BC74-5371E2242388}.Release|Any CPU.Build.0 = Release|Any CPU
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
GlobalSection(ExtensibilityGlobals) = postSolution
SolutionGuid = {21362C82-333C-4D3F-82C0-6662721FD81D}
EndGlobalSection
EndGlobal
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<OutputType>Exe</OutputType>
<TargetFramework>net8.0</TargetFramework>
<ImplicitUsings>enable</ImplicitUsings>
<Nullable>enable</Nullable>
</PropertyGroup>
<ItemGroup>
<Compile Include="..\..\Shared\Graph.cs" Link="Graph.cs" />
<Compile Include="..\..\Shared\GraphCirculant.cs" Link="GraphCirculant.cs" />
<Compile Include="..\..\Shared\GraphMesh.cs" Link="GraphMesh.cs" />
<Compile Include="..\..\Shared\GraphTorus.cs" Link="GraphTorus.cs" />
<Compile Include="..\..\Shared\IRectangleLike.cs" Link="IRectangleLike.cs" />
<Compile Include="..\..\Shared\IRoundLike.cs" Link="IRoundLike.cs" />
<Compile Include="..\..\Shared\ProjectGenerator.cs" Link="ProjectGenerator.cs" />
<Compile Include="..\..\Shared\ProjectSettings.cs" Link="ProjectSettings.cs" />
<Compile Include="..\..\Shared\Settings.cs" Link="Settings.cs" />
</ItemGroup>
<ItemGroup>
<PackageReference Include="Npgsql" Version="9.0.3" />
<PackageReference Include="System.Management" Version="9.0.2" />
<PackageReference Include="System.Security.Cryptography.ProtectedData" Version="9.0.2" />
</ItemGroup>
</Project>
using System;
using System.Diagnostics;
using System.Reflection.Metadata;
using System.Text.Json;
using System.Xml.Linq;
namespace HDLNoCGen
{
static class Program
{
static void finish_job (string json_location, ProjectSettings project_settings)
{
string json = JsonSerializer.Serialize<ProjectSettings>(project_settings, new JsonSerializerOptions { WriteIndented = true });
File.WriteAllText(json_location, json);
Environment.Exit(0);
}
static void Main(string[] args)
{
string location = "C:/Users/Serha/Desktop/kal";
string name = "kal";
string topology = "";
List<int> generators = new List<int>();
string queue_type = "pointer";
string queue_position = "front";
string arbiter_type = "round_robin";
string algorithm = "xy";
int info_width = 8;
int queue_length = 4;
bool create_verilog = false;
Graph graph = null;
router_options parameters = new router_options();
string graph_filename = "";
CancellationTokenSource GeneralPurposeCancellationTokenSource = new CancellationTokenSource();
CancellationToken GeneralPurposeCancellationToken = GeneralPurposeCancellationTokenSource.Token;
try
{
for (int i = 0; i < args.Length; i++)
{
switch (args[i])
{
case "-l":
case "--location":
location = args[++i];
break;
case "-n":
case "--name":
name = args[++i];
break;
case "c":
topology = "c";
break;
case "m":
topology = "m";
break;
case "t":
topology = "t";
break;
case "--queue_type":
queue_type = args[++i];
break;
case "--queue_position":
queue_position = args[++i];
break;
case "--arbiter_type":
arbiter_type = args[++i];
break;
case "--algorithm":
algorithm = args[++i];
break;
case "--info_width":
try
{
info_width = Convert.ToInt32(args[++i]);
}
catch (Exception e)
{
Console.WriteLine("--info_width must be a number");
Environment.Exit(1);
}
break;
case "--queue_length":
try
{
queue_length = Convert.ToInt32(args[++i]);
}
catch (Exception e)
{
Console.WriteLine("--queue_lenght must be a number");
Environment.Exit(1);
}
break;
case "-v":
case "--verilog":
create_verilog = true;
break;
default:
try
{
generators.Add(Convert.ToInt32(args[i]));
}
catch (Exception e)
{
Console.WriteLine($"Argument {args[i]} is invalid");
}
break;
}
}
}
catch (IndexOutOfRangeException e)
{
Console.WriteLine("No argument after an option that requires an argument");
Environment.Exit(1);
}
string metadata_location = $"{location}/{name}_metadata.json";
string project_settings_json = File.ReadAllText(metadata_location);
ProjectSettings projectSettings = JsonSerializer.Deserialize<ProjectSettings>(project_settings_json);
switch (topology)
{
case "c":
graph = new GraphCirculant();
break;
case "m":
graph = new GraphMesh();
break;
case "t":
graph = new GraphTorus();
break;
default:
Console.WriteLine($"Topology {topology} does not exit");
Environment.Exit(1);
break;
}
graph.InstallGenerators(generators, GeneralPurposeCancellationToken);
graph_filename += $"{info_width}_bit";
switch (graph.graphId)
{
case GraphType.Circulant:
graph_filename += "__circulant";
graph_filename += $"_{graph.node_count}_" + String.Join("_", graph.generators.Slice(0, graph.generators.Count - 1).Select(s => $"{s}"));
break;
case GraphType.Mesh:
graph_filename += "__mesh";
graph_filename += $"_{graph.node_count}_" + String.Join("_", graph.generators.Select(s => $"{s}"));
break;
case GraphType.Torus:
graph_filename += "__torus";
graph_filename += $"_{graph.node_count}_" + String.Join("_", graph.generators.Select(s => $"{s}"));
break;
default:
Console.WriteLine($"Graph type {graph.graphId} was not implemented into this switch statement.");
Environment.Exit(1);
break;
}
switch (queue_type)
{
case "index":
parameters.queue_type = RouterOptions.Queue_types.Index;
graph_filename += $"__indexQueue_{queue_length}_long";
break;
case "pointer":
parameters.queue_type = RouterOptions.Queue_types.Pointer;
graph_filename += $"__pointerQueue_{queue_length}_long";
break;
case "line":
parameters.queue_type = RouterOptions.Queue_types.Line;
graph_filename += $"__lineQueue_{queue_length}_long";
break;
default:
Console.WriteLine($"Queue type '{queue_length}' does not exist. It should be either 'index', 'pointer' or 'line'.");
Environment.Exit(1);
break;
}
switch (queue_position)
{
case "front":
parameters.queue_position = RouterOptions.Queue_position.Front;
graph_filename += "_front";
break;
case "rear":
parameters.queue_position = RouterOptions.Queue_position.Rear;
graph_filename += "_rear";
break;
default:
Console.WriteLine($"Queue position '{queue_position}' does not exist. It should be either 'front' or 'rear'.");
Environment.Exit(1);
break;
}
switch (arbiter_type)
{
case "round_robin":
parameters.arbiter_type = RouterOptions.Arbiter_types.Round_Robin;
graph_filename += "__arbRoundRobin";
break;
default:
Console.WriteLine($"Arbiter type '{queue_position}' does not exist. It should be either 'front' or 'rear'.");
Environment.Exit(1);
break;
}
switch (algorithm)
{
case "xy":
graph_filename += "__xy";
switch (graph.graphId)
{
case GraphType.Mesh:
parameters.algorithm = RouterOptions.Algorithm.XY;
break;
case GraphType.Torus:
parameters.algorithm = RouterOptions.Algorithm.XY;
break;
default:
Console.WriteLine($"Graph type {graph.graphId} was not implemented into this switch statement.");
Environment.Exit(1);
break;
}
break;
case "ga":
parameters.algorithm = RouterOptions.Algorithm.GA;
graph_filename += "__ga";
break;
default:
Console.WriteLine($"Algorithm '{algorithm}' does not exist. It should be either 'xy' or 'ga'.");
Environment.Exit(1);
break;
}
switch (graph.graphId)
{
case GraphType.Circulant:
parameters.packet_width = 1 + graph.get_bits(graph.node_count) + info_width;
break;
case GraphType.Mesh:
case GraphType.Torus:
parameters.packet_width = 1 + 2 * graph.get_bits(generators[1]) + info_width;
break;
}
parameters.queue_length = queue_length;
parameters.info_width = info_width;
graph.parameters = parameters;
string graph_json = "";
switch (graph.graphId)
{
case GraphType.Circulant:
graph_json = JsonSerializer.Serialize<GraphCirculant>(graph as GraphCirculant, new JsonSerializerOptions { WriteIndented = true });
break;
case GraphType.Mesh:
graph_json = JsonSerializer.Serialize<GraphMesh>(graph as GraphMesh, new JsonSerializerOptions { WriteIndented = true });
break;
case GraphType.Torus:
graph_json = JsonSerializer.Serialize<GraphTorus>(graph as GraphTorus, new JsonSerializerOptions { WriteIndented = true });
break;
}
using (StreamWriter sw = new StreamWriter($"{location}/{name}_graph_object_serialized.json"))
{
sw.Write(graph_json);
}
projectSettings.graphVerilogMetadata.graphSerialized = true;
if (!create_verilog)
{
finish_job(metadata_location, projectSettings);
}
Tuple<string, Process, Process> preparation_result = ProjectGenerator.routerPreparation(graph, $"{name}_NoC_description", location, parameters);
string verilog_path = preparation_result.Item1;
Process compile_process = preparation_result.Item2;
Process simulate_process = preparation_result.Item3;
graph.createNoC(verilog_path, parameters);
projectSettings.graphVerilogMetadata.verilogGenerated = true;
finish_job(metadata_location, projectSettings);
}
}
}
\ No newline at end of file
{
"profiles": {
"Graph_verilog_generator": {
"commandName": "Project",
"commandLineArgs": "-l D:/kal -n kal m 3 3 --queue_type pointer --queue_position front --arbiter_type round_robin --algorithm xy --info_width 8 --queue_length 16 -v"
}
}
}
\ No newline at end of file
{
"mesh": {
"xy": {
"front": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_X, input[`CS-1:0] router_Y",
"c#_splitter",
"algorithm XY(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(outputs),",
".router_X(router_X), .router_Y(router_Y),",
".availability_signals_in(signals_in), .shift_signals(shift_signals));"
],
"rear": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_X, input[`CS-1:0] router_Y",
"c#_splitter",
"algorithm XY(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(algotihm_to_queue),",
".router_X(router_X), .router_Y(router_Y),",
".availability_signals_in(availability_signals), .shift_signals(signals_out));"
]
}
},
"torus": {
"xy": {
"front": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_X, input[`CS-1:0] router_Y",
"c#_splitter",
"algorithm XY(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(outputs),",
".router_X(router_X), .router_Y(router_Y),",
".availability_signals_in(signals_in), .shift_signals(shift_signals));"
],
"rear": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_X, input[`CS-1:0] router_Y",
"c#_splitter",
"algorithm XY(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(algotihm_to_queue),",
".router_X(router_X), .router_Y(router_Y),",
".availability_signals_in(availability_signals), .shift_signals(signals_out));"
]
}
},
"circulant": {
"ga": {
"front": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_no",
"c#_splitter",
"algorithm GA(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(outputs),",
".router_no(router_no),",
".availability_signals_in(signals_in), .shift_signals(shift_signals));"
],
"rear": [
"input clk,",
"input[0:`PL-1] inputs[0:`REN-1], output[0:`PL-1] outputs[0:`REN-1],",
"input signals_in[0:`REN-1], output signals_out[0:`REN-1],",
"input[`CS-1:0] router_no",
"c#_splitter",
"algorithm GA(",
".from_arbiter(arbiter_to_algorithm), .shift(shift), .outputs(algotihm_to_queue),",
".router_no(router_no),",
".availability_signals_in(availability_signals), .shift_signals(signals_out));"
]
}
}
}
\ No newline at end of file
`ifndef _noc_parameters_svh_
`define _noc_parameters_svh_
`define PL {0}// length of datapack
`define CS {1} // size of single coordinate part
`define RN {2} // number of routers in network
`endif
`ifndef _noc_CIRCULANT_parameters_svh_
`define _noc_CIRCULANT_parameters_svh_
`define GENERATICS {0} // generatics
// GA
`define LT {1} // LT - long throw - length of the long edge
`endif
\ No newline at end of file
`ifndef _noc_XY_parameters_svh_
`define _noc_XY_parameters_svh_
`define X {0} // number of routers in network on X axis
`define Y {1} // number of routers in network on Y axis
`endif
`ifndef _queue_parameters_svh_
`define _queue_parameters_svh_
`include "inc/noc.svh"
`define EN {0} // number of queue entries
`define EN_B {1} // number of bits required to encode queue entries
`endif
`ifndef _router_parameters_svh_
`define _router_parameters_svh_
`include "inc/noc.svh"
`define REN {0} // number of router entries
`define REN_B {1} // number bits required to eoncode router entries
`endif
`include "inc/noc.svh"
`include "inc/noc_CIRCULANT.svh"
`include "src/router.sv"
module noc(
input clk,
output[0:`PL-1] core_inputs[0:`RN-1],
input[0:`PL-1] core_outputs[0:`RN-1],
input core_availability_signals_out[0:`RN-1],
output core_availability_signals_in[0:`RN-1]
);
localparam[0:`CS*(`REN-1)-1] generatics = `GENERATICS;
wire [0:`PL-1] inputs[0:`RN-1][0:`REN-1];
wire availability_signals[0:`RN-1][0:`REN-1];
generate
genvar router_iterator;
for (router_iterator = 0; router_iterator < `RN; router_iterator = router_iterator + 1)
begin : routers
wire [0:`PL-1] outputs [0:`REN-1];
wire availability_signals_in [0:`REN-1];
assign core_inputs[router_iterator] = outputs[0];
assign inputs[router_iterator][0] = core_outputs[router_iterator];
assign availability_signals_in[0] = core_availability_signals_out[router_iterator];
assign core_availability_signals_in[router_iterator] = availability_signals[router_iterator][0];
genvar generatic_iterator;
for (generatic_iterator = 0; generatic_iterator < `REN-1; generatic_iterator = generatic_iterator + 1) begin : generatics_gen
if (generatics[generatic_iterator * `CS : (generatic_iterator+1) * `CS - 1] + router_iterator >= `RN) begin
localparam int next = generatics[generatic_iterator * `CS : (generatic_iterator+1) * `CS - 1] + router_iterator - `RN;
assign inputs[next][`REN-generatic_iterator-1] = outputs[generatic_iterator+1];
assign availability_signals_in[generatic_iterator+1] = availability_signals[next][`REN-generatic_iterator-1];
end else begin
localparam int next = generatics[generatic_iterator * `CS : (generatic_iterator+1) * `CS - 1] + router_iterator;
assign inputs[next][`REN-generatic_iterator-1] = outputs[generatic_iterator+1];
assign availability_signals_in[generatic_iterator+1] = availability_signals[next][`REN-generatic_iterator-1];
end
end
wire [0:`PL-1] input_router[0:`REN-1];
wire avail_router[0:`REN-1];
wire [`CS-1:0] router_no = router_iterator;
genvar i;
for (i = 0; i < `REN; i = i + 1)
begin : wire_crutch_entries
assign input_router[i] = inputs[router_iterator][i];
assign availability_signals[router_iterator][i] = avail_router[i];
end
router router(
.clk(clk),
.inputs(input_router), .outputs(outputs),
.signals_out(avail_router), .signals_in(availability_signals_in),
.router_no(router_no)
);
end
endgenerate
endmodule
`include "inc/noc.svh"
`include "inc/noc_XY.svh"
`include "src/router.sv"
module noc(
input clk,
output[0:`PL-1] core_inputs[0:`Y-1][0:`X-1],
input[0:`PL-1] core_outputs[0:`Y-1][0:`X-1],
input core_availability_signals_out[0:`Y-1][0:`X-1],
output core_availability_signals_in[0:`Y-1][0:`X-1]
);
wire [0:`PL-1] inputs[0:`Y + 1][0:`X + 1][0:`REN-1];
wire availability_signals[0:`Y + 1][0:`X + 1][0:`REN-1];
generate
genvar i, j;
for (i = 0; i <= `Y; i = i + 1)
begin : init_avail_Y
for (j = 0; j < `REN; j = j + 1)
begin : init_avail_REN_1
assign availability_signals[i][0][j] = 1;
assign availability_signals[i][`X + 1][j] = 1;
end
end
for (i = 0; i <= `X; i = i + 1)
begin : init_avail_X
for (j = 0; j < `REN; j = j + 1)
begin : init_avail_REN_2
assign availability_signals[0][i][j] = 1;
assign availability_signals[`Y + 1][i][j] = 1;
end
end
for (i = 1; i <= `X; i = i + 1)
begin : init_packet_X
assign inputs[1][i][1] = 0;
assign inputs[`Y][i][3] = 0;
end
for (i = 1; i <= `Y; i = i + 1)
begin : init_packet_Y
assign inputs[i][1][4] = 0;
assign inputs[i][`X][2] = 0;
end
endgenerate
generate
genvar router_Y_iterator, router_X_iterator;
for (router_Y_iterator = 1; router_Y_iterator <= `Y; router_Y_iterator = router_Y_iterator + 1)
begin : routers_Y
for (router_X_iterator = 1; router_X_iterator <= `X; router_X_iterator = router_X_iterator + 1)
begin : routers_X
assign core_availability_signals_in[router_Y_iterator-1][router_X_iterator-1] = availability_signals[router_Y_iterator][router_X_iterator][0];
localparam lower = router_Y_iterator + 1;
localparam right = router_X_iterator + 1;
localparam upper = router_Y_iterator - 1;
localparam left = router_X_iterator - 1;
wire[0:`PL-1] outputs[0:`REN-1];
assign core_inputs[router_Y_iterator-1][router_X_iterator-1] = outputs[0];
assign inputs[upper][router_X_iterator][3] = outputs[1];
assign inputs[router_Y_iterator][right][4] = outputs[2];
assign inputs[lower][router_X_iterator][1] = outputs[3];
assign inputs[router_Y_iterator][left][2] = outputs[4];
wire signals_in[0:`REN-1];
assign signals_in[0] = core_availability_signals_out[router_Y_iterator-1][router_X_iterator-1];
assign signals_in[1] = availability_signals[upper][router_X_iterator][3];
assign signals_in[2] = availability_signals[router_Y_iterator][right][4];
assign signals_in[3] = availability_signals[lower][router_X_iterator][1];
assign signals_in[4] = availability_signals[router_Y_iterator][left][2];
router router(
.clk(clk),
.inputs(inputs[router_Y_iterator][router_X_iterator]), .outputs(outputs),
.signals_out(availability_signals[router_Y_iterator][router_X_iterator]), .signals_in(signals_in),
.router_Y(router_Y_iterator - 1), .router_X(router_X_iterator - 1)
);
assign inputs[router_Y_iterator][router_X_iterator][0] = core_outputs[router_Y_iterator-1][router_X_iterator-1];
end
end
endgenerate
endmodule
\ No newline at end of file
`include "inc/noc.svh"
`include "inc/noc_XY.svh"
`include "src/router.sv"
module noc(
input clk,
output[0:`PL-1] core_inputs[0:`Y-1][0:`X-1],
input[0:`PL-1] core_outputs[0:`Y-1][0:`X-1],
input core_availability_signals_out[0:`Y-1][0:`X-1],
output core_availability_signals_in[0:`Y-1][0:`X-1]
);
wire [0:`PL-1] inputs[0:`Y-1][0:`X-1][0:`REN-1];
wire availability_signals[0:`Y-1][0:`X-1][0:`REN-1];
generate
genvar router_Y_iterator, router_X_iterator;
for (router_Y_iterator = 0; router_Y_iterator < `Y; router_Y_iterator = router_Y_iterator + 1)
begin : routers_Y
for (router_X_iterator = 0; router_X_iterator < `X; router_X_iterator = router_X_iterator + 1)
begin : routers_X
assign core_availability_signals_in[router_Y_iterator][router_X_iterator] = availability_signals[router_Y_iterator][router_X_iterator][0];
localparam lower = router_Y_iterator == `Y-1 ? 0 : router_Y_iterator + 1;
localparam right = router_X_iterator == `X-1 ? 0 : router_X_iterator + 1;
localparam upper = router_Y_iterator == 0 ? `Y-1 : router_Y_iterator - 1;
localparam left = router_X_iterator == 0 ? `X-1 : router_X_iterator - 1;
wire[0:`PL-1] outputs[0:`REN-1];
assign core_inputs[router_Y_iterator][router_X_iterator] = outputs[0];
assign inputs[upper][router_X_iterator][3] = outputs[1];
assign inputs[router_Y_iterator][right][4] = outputs[2];
assign inputs[lower][router_X_iterator][1] = outputs[3];
assign inputs[router_Y_iterator][left][2] = outputs[4];
wire signals_in[0:`REN-1];
assign signals_in[0] = core_availability_signals_out[router_Y_iterator][router_X_iterator];
assign signals_in[1] = availability_signals[upper][router_X_iterator][3];
assign signals_in[2] = availability_signals[router_Y_iterator][right][4];
assign signals_in[3] = availability_signals[lower][router_X_iterator][1];
assign signals_in[4] = availability_signals[router_Y_iterator][left][2];
router router(
.clk(clk),
.inputs(inputs[router_Y_iterator][router_X_iterator]), .outputs(outputs),
.signals_out(availability_signals[router_Y_iterator][router_X_iterator]), .signals_in(signals_in),
.router_Y(router_Y_iterator), .router_X(router_X_iterator)
);
assign inputs[router_Y_iterator][router_X_iterator][0] = core_outputs[router_Y_iterator][router_X_iterator];
end
end
endgenerate
always @(posedge clk)
begin
end
endmodule
`include "inc/noc.svh"
`include "inc/noc_CIRCULANT.svh"
`include "noc/noc.sv"
module toplevel (
input clk,
input[0:`PL-1] packet,
input[`CS-1:0] core_NO,
input core_availability_signals_out[0:`RN-1],
output core_availability_signals_in[0:`RN-1],
output wire[0:1] core_inputs_2_bits[0:`RN-1]
);
wire[0:`PL-1] core_inputs[0:`RN-1];
wire[0:`PL-1] core_outputs[0:`RN-1];
generate
genvar i;
for (i = 0; i < `RN; i = i + 1)
begin : bool_grid
assign core_inputs_2_bits[i] = {core_inputs[i][0], ^core_inputs[i]};
end
endgenerate
dataSelector selector(.clk(clk), .packet(packet), .core_NO(core_NO), .core_outputs(core_outputs));
noc noc(
.clk(clk),
.core_inputs(core_inputs),
.core_outputs(core_outputs),
.core_availability_signals_out(core_availability_signals_out),
.core_availability_signals_in(core_availability_signals_in)
);
endmodule
module dataSelector (
input clk,
input[0:`PL-1] packet,
input[`CS-1:0] core_NO,
output reg[0:`PL-1] core_outputs[0:`RN-1]
);
initial begin
int i;
for (i = 0; i < `RN; i = i + 1)
begin
core_outputs[i] = 0;
end
end
always @(posedge clk) begin
core_outputs[core_NO] <= packet;
end
endmodule
\ No newline at end of file
`include "inc/noc.svh"
`include "inc/noc_XY.svh"
`include "noc/noc.sv"
module toplevel (
input clk,
input[0:`PL-1] packet,
input[`CS-1:0] core_X,
input[`CS-1:0] core_Y,
input core_availability_signals_out[0:`Y-1][0:`X-1],
output core_availability_signals_in[0:`Y-1][0:`X-1],
output wire[0:1] core_inputs_2_bits[0:`Y-1][0:`X-1]
);
wire[0:`PL-1] core_inputs[0:`Y-1][0:`X-1];
wire[0:`PL-1] core_outputs[0:`Y-1][0:`X-1];
generate
genvar i, j;
for (i = 0; i < `Y; i = i + 1)
begin : bool_grid_Y
for (j = 0; j < `X; j = j + 1)
begin : bool_grid_X
assign core_inputs_2_bits[i][j] = {core_inputs[i][j][0], ^core_inputs[i][j]};
end
end
endgenerate
dataSelector selector(.clk(clk), .packet(packet), .core_X(core_X), .core_Y(core_Y), .core_outputs(core_outputs));
noc noc(
.clk(clk),
.core_inputs(core_inputs),
.core_outputs(core_outputs),
.core_availability_signals_out(core_availability_signals_out),
.core_availability_signals_in(core_availability_signals_in)
);
endmodule
module dataSelector (
input clk,
input[0:`PL-1] packet,
input[`CS-1:0] core_X,
input[`CS-1:0] core_Y,
output reg[0:`PL-1] core_outputs[0:`Y-1][0:`X-1]
);
initial begin
int i, j;
for (i = 0; i < `Y; i = i + 1)
begin
for (j = 0; j < `X; j = j + 1)
begin
core_outputs[i][j] = 0;
end
end
end
always @(posedge clk) begin
core_outputs[core_Y][core_X] <= packet;
end
endmodule
\ No newline at end of file
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