Добавил оставшиеся инструкции

digital_devices_sys_design/lab_1/schoolMIPS/src/src/sm_cpu.v

@@ -125,9 +125,14 @@ module sm_control
             { `C_SPEC,  `F_SRL  } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRL;  end
             { `C_SPEC,  `F_SLTU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SLTU; end
             { `C_SPEC,  `F_SUBU } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SUBU; end
+            /*
+            { `C_SPEC,  `F_MUL  } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_MUL; end
+            { `C_SPEC,  `F_SRLV } : begin regDst = 1'b1; regWrite = 1'b1; aluControl = `ALU_SRLV; end
+            */
 
             { `C_ADDIU, `F_ANY  } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ADD;  end
             { `C_LUI,   `F_ANY  } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_LUI;  end
+            { `C_ANDI,  `F_ANY  } : begin regWrite = 1'b1; aluSrc = 1'b1; aluControl = `ALU_ANDI;  end
 
             { `C_BEQ,   `F_ANY  } : begin branch = 1'b1; condZero = 1'b1; aluControl = `ALU_SUBU; end
             { `C_BNE,   `F_ANY  } : begin branch = 1'b1; aluControl = `ALU_SUBU; end
@@ -156,6 +161,11 @@ module sm_alu
             `ALU_SLTU : result = (srcA < srcB) ? 1 : 0;
             `ALU_SUBU : result = srcA - srcB;
             `ALU_BGEZ : result = ($signed(srcA) >= 0) ? 1: 0;
+            `ALU_ANDI : result = srcA & srcB;
+            /*
+            `ALU_MUL  : result = srcA * srcB;
+            `ALU_SRLV : result = srcB >> srcA;
+            */
         endcase
     end
 

digital_devices_sys_design/lab_1/schoolMIPS/src/src/sm_cpu.vh

@@ -16,6 +16,11 @@
 `define ALU_SLTU    3'b100
 `define ALU_SUBU    3'b101
 `define ALU_BGEZ    3'b110
+`define ALU_ANDI    3'b111
+/*
+`define ALU_MUL     3'b111
+`define ALU_SRLV    3'b111
+*/
 
 
 //instruction operation code
@@ -30,6 +35,8 @@
                               //         if (Rs != Rt) PC += (int)offset
 `define C_BGEZ      6'b000001 // I-type, Branch on Greater Than or Equal to Zero
                               //         if (Rs >= 0) PC += (int)offset
+`define C_ANDI      6'b001100 // I-type, Do a bitwise logical AND with a constant
+                              //         if Rt = Rs and Immed                              
 
 //instruction function field
 `define F_ADDU      6'b100001 // R-type, Integer Add Unsigned
@@ -42,4 +49,8 @@
                               //         Rd = (Rs∅ < Rt∅) ? 1 : 0
 `define F_SUBU      6'b100011 // R-type, Unsigned Subtract
                               //         Rd = Rs – Rt
+`define F_MUL       6'b011100 // R-type, Multiply two words 
+                              //         Rd = Rs * Rt
+`define F_SRLV      6'b000000 // R-type, Shift Word Right Logical Variable
+                              //         Rd = Rt >> Rs
 `define F_ANY       6'b??????

digital_devices_sys_design/lab_1/schoolMIPS/src/testbench/testbench.v

@@ -99,9 +99,14 @@ module sm_testbench;
                 { `C_SPEC,  `F_SRL  } : $write ("srl   $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                 { `C_SPEC,  `F_SLTU } : $write ("sltu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
                 { `C_SPEC,  `F_SUBU } : $write ("subu  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                /*
+                { `C_SPEC,  `F_MUL  } : $write ("mul  $%1d, $%1d, $%1d", cmdRd, cmdRs, cmdRt);
+                { `C_SPEC,  `F_SRLV } : $write ("srlv  $%1d, $%1d, $%1d", cmdRd, cmdRt, cmdRs);
+                */
 
                 { `C_ADDIU, `F_ANY  } : $write ("addiu $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
                 { `C_LUI,   `F_ANY  } : $write ("lui   $%1d, %1d",       cmdRt, cmdImm);
+                { `C_ANDI,  `F_ANY  } : $write ("andi  $%1d, $%1d, %1d", cmdRt, cmdRs, cmdImm);
 
                 { `C_BEQ,   `F_ANY  } : $write ("beq   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);
                 { `C_BNE,   `F_ANY  } : $write ("bne   $%1d, $%1d, %1d", cmdRs, cmdRt, cmdImmS + 1);