Branches · 1718 Низкоуровневое моделирование сетей на кристалле / Verilog prototypes · GitLab

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router-dev

8972c73c · Small arbiter modification. Result: 95.82 MHz · Nov 14, 2024

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uart merged

73a24634 · Testbench for the UART module · Jan 17, 2025

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router_publication

6ccbdcbf · Uart merge handled · Jan 24, 2025

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master-patch-7548 merged

6a6354c2 · Update file README.md · Apr 13, 2025

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master default protected

5df403ec · Merge branch 'uart' into 'master' · Apr 13, 2025

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